This invention relates to a method for manufacturing a semiconductor device and in particular a method for manufacturing a semiconductor device having an element area, surrounded by a field insulation layer, in a semiconductor substrate.
Recently, the memory cells of semiconductor devices have a tendency to be made in microminiaturized form so as to enhance, for example, an integration density. The surface area of the semiconductor substrate is divided by the formation of a field insulation layer into a plurality of element areas where corresponding memory cells are formed. Each memory cell is electrically insulated from other memory cells due to the field insulation layer.
An erasable and programmable read only memory (EPROM) includes, for example, n-channel floating gate MOS transistors as memory cells, one of which is shown in FIG. 1. In the arrangement shown in FIG. 1, a field insulation layer 10 is formed on a p-type semiconductor substrate 12 and a p.sup.+ -type region is formed in that portion of the substrate 12 which is located immediately below the field insulation layer 10. Source and drain regions, which are n.sup.+ -type regions 16A and 16B, respectively, are formed in an element area defined by the field insulation layer 10 in contact with the p.sup.+ -type region 14. The element area is covered by an insulation layer 18. A floating gate electrode 20 is formed through an insulation layer 18 on the channel region which lies between the n.sup.+ -type regions 16A and 16B. A control gate electrode 22 is formed on the floating gate electrode 20 on the insulation layer. The insulation layer 24 covers the control gate electrode, floating gate electrode 20 and field insulation layer. Source and drain electrodes 26A and 26B are ohmically connected to the n.sup.+ -type regions 16A and 16B, respectively, through corresponding holes which extend through insulation layers 24 and 18.
In FIG. 1, the p.sup.+ -type region 14 is so provided as to prevent the conductivity type of the substrate 12 from being inverted to an n-type immediately below the field insulation layer 10 due to the fixed charges of the field insulation layer 10 and an electric field resulting from an interconnection layer, not shown, on the insulation layer 24. The occurrence of such an inversion phenomenon causes a short-circuiting current to flow between the n.sup.+ -type regions 16A, 16B of one element area and those of another element area.
In a programming operation in a case where the floating gate MOS transistor is used as the memory cell, a high voltage of about 20 V is applied between the control gate electrode 22 and drain electrode 26B in order to charge the floating gate electrode 20 with hot electrons. The hot electrons are generated between the n.sup.+ -type regions 16A and 16B upon application of the high voltage. In this case, a voltage on the n.sup.+ -type region 16B can be held within a range not exceeding a breakdown voltage between the n.sup.+ -type region 16B and the p.sup.+ -type region 14. In the MOS transistor in FIG. 1, the breakdown voltage between the n.sup.+ -type region 16B and p.sup.+ -type region 14 largely depends upon the impurity concentration level of the p.sup.+ -type region 14. This is because, in order to set the n.sup.+ -type region 16B at a lower resistive value, the n.sup.+ -type region 16B is set to a high impurity concentration level of about 10.sup.20 cm.sup.-3, and because the p.sup.+ -type region is higher in its impurity concentration level than the semiconductor substrate. The impurity concentration level may be about 5.times.10.sup.16 cm.sup.-3 as an upper limit, taking into consideration the fact that a reverse bias voltage of 20 V is applied to the pn junction between the n.sup.+ -type region 16B and the p.sup.+ -type region 14.
There is a tendency of the field insulation layer 10 to be thinly formed due to the microminiaturization of the memory cells. In consequence, there is a high substantial possiblity that an inversion phenomenon will occur in the conductivity type of the p.sup.+ -type region 14 which is located immediately below the field insulation layer 10. This phenomenon can be prevented by further increasing the impurity concentration level of the p.sup.+ -type region 14, as has been done in practice. However, an increase in the impurity concentration level of the p.sup.+ -type region 14 causes a drop in the breakdown voltage between the n.sup.+ -type region 16B and the p.sup.+ -type region 14. If the impurity concentration of the p.sup.+ -type region 14 is set at a level exceeding the above-mentioned upper limit, it is not allowed to apply a voltage of 20 V to the n.sup.+ -type region 16B. From this it may be said that the structure of the memory cell or a floating gate MOS transistor in FIG. 1 is not suitable for the high integration of memory devices.
FIG. 2 shows an already known memory cell, which is the same as the floating gate MOS transistor of FIG. 1 except that an n-type region 28 is formed between a p.sup.+ -type region 14 and an n.sup.+ -type region 16B. This memory cell allows a relatively high breakdown voltage between the n-type region 28 and the p.sup.+ -type region 14.
In the manufacture of the memory cell as shown in FIG. 2 the conventional technique requires two impurity diffusion or ion-implantation steps in forming the n.sup.+ -type region 16B and n-type region 28. Furthermore, a material for use as a mask pattern needs to be subjected to a patterning process in the step of the impurity diffusion. In the memory cell of FIG. 2, the n-type region 28 is located outside the n.sup.+ -type region 16B, requiring a wide element area in comparison with that shown in FIG. 1.